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1. How many PWM generator blocks are there in LM3S1968? What are they? 2. How many independent PWM outputs can be generated on an LM3S1968? 3. List at least two applications for PWM. 4. What does NVIC in a timer stand for? Explain its significance. 5. Where does the counter/timer derive its time period from? 6. Draw the waveforms (square wave) with duty cycles (on) 25%, 50%, 75%.One of the purpose of the lab is to generate a PWM signal in one of the ports using systick timer. a. Given a signal with 1 KHz, find out the time period of each cycle. Find out the time span of the high signal and the low signal given 10%, 20%, 30% and 90% duty cycles. b. We would like to generate a signal with a certain frequency (ex. 100 Hz, 1 KHz, etc.) and certain duty cycle (10%, 20%, etc.), find out the values we need to load into the timer register? Given that the XTAL = 8 MHz.

User Keronda
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Answer:

1) There are three (3) PWM generator blocks in LM3S1968 and they are

  • PWM signal generator
  • ADC trigger selector
  • PWM dead-band generator

2) Two (2) independent PWM outputs can be generated on an LM3S1968

3) Applications for PWM

  • Control Brightness of LED using Duty Cycle control
  • Speed Control of DC Motor

4) NVIC in a timer stand for ; Nested Vectored Interrupt Controller

its significance is that it is used to handle and give priorities to exception and Interrupts

5) The counter/timer derive its time period from counting the output pulses for one cycle which is the duration over which gate is open

Step-by-step explanation:

1) There are three (3) PWM generator blocks in LM3S1968 and they are

  • PWM signal generator
  • ADC trigger selector
  • PWM dead-band generator

2) Two (2) independent PWM outputs can be generated on an LM3S1968

3) Applications for PWM

  • Control Brightness of LED using Duty Cycle control
  • Speed Control of DC Motor

4) NVIC in a timer stand for ; Nested Vectored Interrupt Controller

its significance is that it is used to handle and give priorities to exception and Interrupts

5) The counter/timer derive its time period from counting the output pulses for one cycle which is the duration over which gate is open

6) THE WAVEFORM DIAGRAMS IS ATTACHED BELOW

it can be seen that 50 % rises and goes down at half interval. 75 % goes down at half more of 50% and 25% goes down at half less of 50%

1. How many PWM generator blocks are there in LM3S1968? What are they? 2. How many-example-1
User Qstack
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