Final answer:
In MIPS assembly, to store the 32-bit constant 0x20014924 to register $t1, two instructions, lui and ori, are used. Jump (J-type) instructions can target any address within a 256MB segment, while branch (B-type) instructions have a ±16MB range of the current PC value.
Step-by-step explanation:
To create a 32-bit constant 0x20014924 in MIPS assembly and store it in register $t1, you'll need to use two instructions due to the immediate field being only 16 bits wide. Here is the code to do so:
lui $t1, 0x2001 # Load upper immediate with the upper 16 bits
ori $t1, $t1, 0x4924 # Or immediate with the lower 16 bits, stored in $t1
For the second part of the question regarding the program counter (PC), MIPS assembly does not use PC-relative addressing in jump and link instructions. This ensures that the PC can easily be set to a new location by specifying the desired address directly in the instruction. These instructions can encode a target address within a certain range.
J-type instructions like 'j' and 'jal' have a 26-bit address field, allowing for a jump within the same 256MB segment of the current PC with address bits 28-31 being preserved.
B-type instructions like 'beq' and 'bne' are PC-relative and can typically branch within a ±16MB range from the current PC.
If the PC is at 0x00000000, you cannot reach an address in exercise 2.39 with a single jump instruction because it's likely outside the range of the jump (J-type) instruction. However, if the PC is at 0x1FFFf000, depending on the target address, you might also not be able to use a single B-type instruction if the target is out of the ±16MB range.