Final answer:
10 bits is the maximum size of the op-code field if the instruction has a register operand and a memory address operand. (option c is the correct answer)
Step-by-step explanation:
To calculate the maximum size of the op-code field for an instruction with a register operand and a memory address operand, we need to consider the number of registers and addressing modes. If a CPU has 12 registers and uses 6 addressing modes, the total number of unique combinations for the operands is the product of these values (12 registers × 6 addressing modes = 72 combinations).
To represent 72 unique combinations, we need a binary number with at least 7 bits (2^7 = 128, which is more than enough for 72 combinations). However, the opcode field size is usually chosen to be a power of 2 to simplify the hardware design. Therefore, the next highest power of 2, which is greater than or equal to 7, is 8 (2^8 = 256). However, since we only need 72 combinations, we can use a 7-bit op-code field.
The instruction format would typically have additional bits for other fields (e.g., mode bits, register specifier), so the total size of the instruction might be larger. However, for the op-code field alone, 7 bits are sufficient.
Considering the number of registers and addressing modes, the maximum size of the op-code field for an instruction with a register operand and a memory address operand is 7 bits, making option (c) 10 bits incorrect. The correct answer is (c) 10 bits.