Final answer:
To implement lwr in a RISC architecture like MIPS, it can be treated as a pseudo-instruction and rewritten using existing instructions. The minimum set of instructions would be add, sll, and lw. In the CISC approach, hardware is modified to handle lwr directly, and the percentage of lwrs needed to make it perform better than RISC can be calculated.
Step-by-step explanation:
(a) The RISC approach:
To implement the instruction lwr $ra, $rb($rc) in a RISC architecture like MIPS, we can treat lwr as a pseudo-instruction and rewrite it in terms of existing instructions. The minimum set of instructions to do this would be:
- add $rt, $rb, $rc: This instruction adds the values in registers $rb and $rc and stores the result in $rt.
- sll $rt, $rt, 2: This instruction shifts the value in register $rt left by 2 bits, effectively multiplying it by 4.
- add $rt, $ra, $rt: This instruction adds the value in register $ra to the shifted value in $rt and stores the result in $rt.
- lw $ra, 0($rt): This instruction loads a word from memory at the address specified by $rt into register $ra.
(b) The CISC approach:
In the CISC approach, we would modify the hardware to handle the new instruction lwr directly. To determine the percentage of lwrs that would make the CISC approach perform better than the RISC approach, we need to consider the impact on clock period. Assuming a constant CPI for all instructions, we can calculate the percentage of lwrs needed using the formula:
Percentage of lwrs > (8 / (CPI Increase - 1)) * 100%