Question

Build a register file with 32 32-bit registers with two write ports. You don't need to show any hardware or signals involved with the read ports for this question. The circuit should have the following interface:

- Input write1 (1 bit): if set, activate the first write port; if clear, do not write.
- Input write_data1 (32 bits): data to write.
- Input write_index1 (5 bits): index of the first register to write to.
- Input write2 (1 bit): if set, activate the second write port; if clear, do not write.
- Input write_data2 (32 bits): data to write.
- Input write_index2 (5 bits): index of the second register to write to.
- Input clear: asynchronous reset setting the value of all registers to 0.
- Input clock: clock signal, causing writes to be effective at the falling edge.

Notice that having more than one write port introduces the special case where both write ports are trying to write different values into the same register by setting both write1 and write 2 to 1 , and having equal values for write_index1 and write_index2. In this situation, your implementation should prioritize the first write port, making write_data1 be the value written in the selected register.

Draw a logic diagram for the proposed circuit, and write a detailed description for your design.

Answer 1

The circuit involves 32 32-bit registers with two write ports that handle write requests and prioritize the first port in case of conflict. It uses logical gates, multiplexers, and responds to an asynchronous clear signal and clock signal at the falling edge.

Step-by-step explanation:

Register File Design

To design a register file with 32 32-bit registers and two write ports, we need to create a circuit that manages the write requests and respects their priorities. Each register is controlled by a register enable signal that, when activated, allows data to be written to the register at the falling edge of the clock signal. The write1 and write2 inputs determine whether the write ports are active, and the corresponding write_data and write_index values specify the data to write and which register to write to.

If both write1 and write2 are set to 1, indicating simultaneous writes to the same register (due to identical write_index1 and write_index2 values), we prioritize the first write port. This prioritization can be achieved by implementing a write logic that disables the second write port when the first write port is also writing to the same register.

The clear input is an asynchronous reset that sets all registers to 0. The clock signal determines when the writes occur, with changes happening at its falling edge. The write logic involves the use of logical gates and multiplexers to control which data is written to which register based on the write enable signals and index inputs.