Answer:
Step-by-step explanation:
Once we are given a truth table that specifies the logic states 1 or 0 of the output of the logic circuit for all combinations of the logic states of the given inputs, we select the combinations of the logic states of the inputs for which the output is 1. Then we do ORing of all such combinations. For each such combination we AND the logic states.
We can optimize the formula further by using Karnaugh maps or K-maps that combine two or more combinations into one more generic combination.
Example: Let A and B be the inputs. Y be the output.
A B Y
1 1 0
1 0 0t
0 1 1
0 0 1
This can be expressed as : A' . B' + A' . B
This requires two inverter gates for producing A' and B' from A and B respectively. Then two AND gates are required to produce A' AND B' , and A' AND B. Finally we require an OR gate to produce the output.
To optimize the final circuit, we can combine the last two rows in the truth table, and write it simply as A'. So the final circuit will have only one inverter gate.