Answer:
7
Step-by-step explanation:
The structure of memory chip is given by multiplying the number of rows and column ie M X N
he number of address line required for row decoder is n where M =
or expressed in logarithmic form we have
![n= log_2 M](https://img.qammunity.org/2020/formulas/engineering/college/hzpteusje2anf63g8dc8jtrjl3gock4cea.png)
In this case M=N since number of rows is equal to the number of columns
Therefore,
![M X N= M x M= M^(2)=16 kb=16384 b= 2^(4) * 2^(10)= 2^(14)](https://img.qammunity.org/2020/formulas/engineering/college/lc295mk13l99mmd7qt63tbyhnq1pru8ptb.png)
![M^(2)= 2^(14)](https://img.qammunity.org/2020/formulas/engineering/college/ugnxzil6lbxcj4yle30hbyhahq516nfe2o.png)
Therefore,
M=128
Since
![n=log_2 M](https://img.qammunity.org/2020/formulas/engineering/college/himv67md2bs6wfrig7b3x7xu0ar9o0vmr5.png)
![n=log_2 128=7](https://img.qammunity.org/2020/formulas/engineering/college/ahr23chfmzq0rgpdgljs47nkw72lm0hblx.png)
Therefore, address lines should be at least 7