Question

Assume you wish to transfer an n B file along a path composed of the source, destination, 7 point-to-point links, and 5 switches. Suppose each link has a propagation delay of 2ms and a bandwidth of 4Mbps, and that the switches support both circuit and packet switching. Thus, you can either break the file up into 1-KB packets or set up a circuit through the switches and send the file as one contiguous bitstream. Suppose that packets have 24B of packet header information and 1000B of payload, store-and-forward packet processing at each switch incurs a 1-ms delay after the packet had been completely received, packets may be sent continuously without waiting for acknowledgments, and circuit setup requires a 1-KB message to make one round trip on the path, incurring a 1-ms delay at each switch after the message has been completely received. Assume switches introduce no delay to data traversing a circuit. You may also assume that filesize is a multiple of 1000B.A. For what filesize n B is the total number of bytes sent across the network less for circuits than for packets?

B. For what filesize n B is the total latency incurred before the entire file arrives at the destination less for circuits than for packets?C. How sensitive are these results to the number of switches along the path? To the bandwidth of the links? To the ratio of packet size to packet header size?D. How accurate do you think this model of the relative merits of circuits and packets is? Does it ignore important considerations that discredit one or the other approach? If so, what are they?

Answer 1

a) n > 8600 bytes

b) 9500 bytes

c) The results calculated above a very sensitive to the ratio of the packet size to the packet header

d) the model is accurate because N > 9500 bytes

Step-by-step explanation:

A) The filesize n B

no of bytes transferred = no of packets * packet size

= ( n / 1000 ) * 1024

circuit switching

number of bytes transferred = file size + two packets

= n + (2 * 1024)

comparing both equations

= n + (2048) < ( n/1000) * 1024

= 24 * n / 1000 > 2048

hence: n > 8600 bytes

B ) The filesize n B is the total latency incurred before the entire file arrives at the destination less for circuits than for packets

packet switching :

Latency = ( n/1000 ) * ( 1024 * 8 bits/4 Mbps ) + 3 * ( 1024 * 8 bits / 4 Mbps) s + (3 * 1 ms + 4 * 2 ms)

= ( n * 2 * 1026 / 10^6 )ms + 6.144 + 11

Circuit switching

Latency = ( n * 8 bits/ 4 Mbps ) s + 4 * 2 ms + 2 * ( 4 * 1024 * 8/4 mbps + 3 * 1 ms + 4 * 2 ms )

= n * 2*10 n3 / 10^6 ms + 8 + 2 * ( 19.1920 )

= 2n / 10 n3 + 38.3840

therefore for n to meet the requirement

( n * 2 * 1024 / 10 n6 ) ms + 17.144 > 2n / 10 n3 + 38.384

hence N > 9500 BYTES

C ) The results calculated above a very sensitive to the ratio of the packet size to the packet header

D) The model is accurate because N > 9500 bytes

and It doesn't ignore any important considerations