Question

Consider a pipelined processor with just one level of cache. assume that in the absence of memory delays, the baseline cpi of this processor is 2. now assume that the percentage of memory instructions in a typical program executed on this cpu is 50% and the memory access latency is 150 cycles. assuming that the i-cache delays are already accounted for in the baseline cpi, consider the following two alternatives for the d-cache design:

alternative 1: a small d-cache with a hit rate of 94% and a hit access time of 1 cycle (assume that no additional cycles on top of the baseline cpi are added to the execution on a cache hit in this case).
alter tive 2: a larger d-cache with a hit rate of 98% and the hit access time of 2 cycles (assume that every memory instruction that hits into the cache adds one additional cycle on top of the baseline cpi).
a) [5%] estimate the cpi metric for both of these designs and determine which of these two designs provides better performance. explain your answers
b) [5%] repeat part (a), but now assume that the memory access latency is reduced to 50 cycles.
c) [5%] repeat part (b), but now assume that the l2 cache is also added to the system with the hit rate of 75% and access latency of 10 cycles.

Answer 1

The computation of CPI entails assessing the average memory access time for each cache design alternative. Alternative 1 results in a CPI of 6.97, while Alternative 2 yields a better performance with a CPI of 4.98. When adjusting for changes in memory latency and adding an L2 cache, these figures will change, generally suggesting improved performance.

Step-by-step explanation:

The student's question pertains to the calculation of the CPI (cycles per instruction) for a pipelined processor with different cache design alternatives and the impact of memory access latency on the processor's performance.

Alternative 1: Small D-Cache (94% hit rate, 1 cycle hit time)

The average memory access time (AMAT) for this cache design can be found using the formula AMAT = (Hit Time * Hit Rate) + (Miss Rate * Miss Penalty). With a 94% hit rate and 150 cycle miss penalty, AMAT = (1 cycle * 0.94) + (0.06 * 150 cycles) = 0.94 cycles + 9 cycles = 9.94 cycles. Since 50% of instructions are memory accesses, the additional memory CPI = 0.5 * 9.94 = 4.97 cycles.

Add this to the baseline CPI of 2 gives 6.97 cycles per instruction for Alternative 1.

Alternative 2: Larger D-Cache (98% hit rate, 2 cycles hit time)

For Alternative 2, the AMAT calculation is similar, but includes an extra cycle for cache hits: AMAT = (Hit Time * Hit Rate) + (Miss Rate * Miss Penalty) = (2 cycles * 0.98) + (0.02 * 150 cycles) = 1.96 cycles + 3 cycles = 4.96 cycles. With the additional cycle per cache hit, the adjusted memory CPI becomes 0.5 * (4.96 + 1) = 2.98 cycles.

Adding this to the baseline CPI of 2 gives 4.98 cycles per instruction for Alternative 2.

Comparing the two alternatives, Alternative 2 provides better performance with a lower estimated CPI.

Reducing Memory Latency to 50 cycles

If the memory access latency is reduced to 50 cycles, the AMAT and resulting CPI would be recalculated for each alternative, generally resulting in better performance for both options due to the lower miss penalty.

Adding an L2 Cache (75% hit rate, 10 cycles latency)

With the introduction of an L2 cache with a 75% hit rate and 10 cycle latency, the calculation of AMAT must now include the likelihood of hitting in the L2 cache after missing in the D-cache. This new layer of caching will further lower the effective memory access latency and consequently, improve the overall performance.

Answer 2

Alternative 1:A small D-cache with a hit rate of 94% and a hit access time of 1 cycle (assume that no additional cycles on top of the baseline CPI are added to the execution on a cache hit in this case).Alternative 2: A larger D-cache with a hit rate of 98% and the hit access time of 2 cycles (assume that every memory instruction that hits into the cache adds one additional cycle on top of the baseline CPI). a)[10%] Estimate the CPI metric for both of these designs and determine which of these two designsprovides better performance. Explain your answers!CPI = # Cycles / # InsnLet X = # InsnCPI = # Cycles / XAlternative 1:# Cycles = 0.50*X*2 + 0.50*X(0.94*2 + 0.06*150)CPI= 0.50*X*2 + 0.50*X(0.94*2 + 0.06*150) / X1= X(0.50*2 + 0.50(0.94*2 + 0.06*150) ) / X= 0.50*2 + 0.50(0.94*2 + 0.06*150)= 6.44Alternative 2:# Cycles = 0.50*X*2 + 0.50*X(0.98*(2+1) + 0.02*150)CPI= 0.50*X*2 + 0.50*X(0.98*(2+1) + 0.02*150) / X2= X(0.50*2 + 0.50(0.98*(2+1) + 0.02*150)) / X= 0.50*2 + 0.50(0.98*(2+1) + 0.02*150)= 3.97Alternative 2 has a lower CPI, therefore Alternative 2 provides better performance.