Answer:
See explanation.
Step-by-step explanation:
Given:
Instruction miss rate = I-cache miss rate = 5% = 0.05
Data miss rate = D-cache miss rate = 4% = 0.04
CPI (without including the stall cycles) = 1.5
Miss Penalty = 40 ns × 3 GHz = 120 cycles
load and store instructions = 25% = 0.25
hit time = 1 clock cycle
a. Compute the number of stall cycles per instruction
Instruction miss cycles = I-cache miss rate * miss penalty
= 0.05 * 120
= 6
Data miss cycles = D-cache miss rate * miss penalty * load and store
instructions
= 0.04 * 120 * 0.25
= 1.2
Total memory stall cycles = Instruction miss cycles + Data miss cycles
= 6 + 1.2
= 7.2
number of stall cycles per instruction = 7.2
b. Compute the overall (cycle per instruction) CPI
CPI (stall) = 1.5 + 7.2
= 8.7
Ideal CPU = CPU time with stalls / CPU time with perfect cache
= I x CPI (stall) x Clock cycle/ I x CPI x Clock cycle
= 8.7 / 1.5
= 5.8
c. Compute the average memory access time (AMAT) in ns.
Combined misses per instruction = 0.05 + 0.25 * 0.04 = 0.06
Combined Miss Rate = Combined misses per I/ 1.25 access per I
Combined Miss Rate = 0.06 / 1.25 = 0.048
Average Memory Access time (AMAT) = Hit time + Miss rate × Miss penalty
= 1 + 0.048 * 120
= 6.7
= 6.76 cycles
= 6.76 / 3
= 2.253 ns
AMAT = 2.253 ns