Part 2: a) Write VHDL code for a top module that invokes necessary components to display the four decimal digits on four seven-segment displays of a NEXYX 4 FPGA. The top module takes the 100 MHz FPGA clock, a reset signal, an enabler signal as the inputs. b) Makes necessary changes in a constraint file to implement your design on the FPGA and present only the uncommented parts of the constraint file in your exam script.