Question

Design a ROM of size 64X8 bit in VHDL. Your ROM takes as input an address and a clock and output the content of the ROM at the corresponding input address on the rising edge of the clock. (2 Pts)

Answer 1

Number of Address lines to address all locations of 64x8 ROM

log₂(64) = log₂2⁶ = 6

Number of address lines Required = 6

Number of bits in each location = 8