A non-trivial system is often composed of multiple components working together. The individual components may have different delays for different input data. In order to send the data to a component only when it is idle, or read its output only when it is ready, certain communication protocol is needed. In this exercise, create a VHDL model with a master and a slave communicating with each other following a certain protocol. The slave implements the binary division (Refer to the binary divider design in Listing 6.4 in Chu's book). The master generates two numbers which are sent to the slave for division. Then it waits until the results returned from the slave. Once the results form the slave are available, the master checks the correctness of the results while producing a new pair of numbers for the slave. (a) Develop the master and slave with proper interface. In this assignment, the slave should be developed as a synthesizable model, while the master is described a test generation component. (b) Connect them in a testbench, and simulate it. (c) Simulate your design such that the master and slave can communicate correctly.