Question

Consider the interrupt mechanism we discussed in class.Suppose we make the following change:when the interrupt occurs, the hardware will save only PC value(not the PSW value). Also, the RTI (return from interrupt)instruction will reload only the PC register, not the PSW register.Service routine would use 3 new machine instructions to save old PSW onto control stack, load new PSW from interrupt vector, and reload old PSW from control stack.There are no other changes.Explain what problem will arise due to this change (in less than50 words).

Answer 1

Shifting the responsibility of managing the PSW to the software via service routines increases complexity, raises the potential for PSW management errors, and leads to increased interrupt latency due to additional required instructions.

Step-by-step explanation:

If the interrupt mechanism of a computer system is modified such that the hardware saves only the Program Counter (PC) and not the Processor Status Word (PSW), and the Return from Interrupt (RTI) instruction only reloads the PC, the responsibility of managing the PSW is shifted to the software. The service routine would need to perform additional steps to manually save and restore the PSW using new machine instructions. This change can introduce problems such as increased complexity in the interrupt service routines, potential for errors in PSW management, and increased interrupt latency as extra instructions must be executed during an interrupt.

Answer 2

Answer explained below

Step-by-step explanation:

The act of coming back from AN interrupt, for example via the RTI instruction, can 'automatically' cause the previous laptop and standing register values to be fixed.

Note: coming back from AN interrupt handler doesn't clear the interrupt event unfinished indication, therefore the interrupt handler, before exiting has to modify the acceptable register otherwise the flow of execution can like a shot reenter the interrupt handler.

The interrupt handler needs to, upon entry, push the other registers that it modifies and, once able to exit, restore them.

Only interrupts of a lower priority area unit blocked by the interrupt event amusing the laptop to the acceptable interrupt handler. Blocked, not disabled.on some CPUs, for example most DSPs, there also are code interrupts which will be triggered by AN process. this can be typically employed by hardware interrupt handlers to trigger the info process when some quantity of knowledge has been input/saved during a buffer. This separates the I/O from the process thereby sanctionative the hardware interrupt event handler to be fast and still have the info processed during a timely manner