Question

Assume we have a computer where the clocks per instruction (CPI) is 1.0 when all memory accesses hit in the cache. The only data accesses are loads and stores, and these total take 40% of the instructions. If the miss penalty is 200 clock cycles and the miss rate is 2% for I-Cache and 5% for D-cache, how much faster would the computer be if all instructions were cache hits

Answer 1

To calculate the speed improvement when all instructions are cache hits, calculate the average CPI with cache misses and the average CPI with all cache hits. Speedup = Average CPI with cache misses / Average CPI with all cache hits. The computer would be approximately 6.857 times faster if all instructions were cache hits.

Step-by-step explanation:

To calculate the speed improvement when all instructions are cache hits, we need to determine the average CPI with cache misses and the average CPI with all cache hits.

The average CPI is the sum of the product of CPI and the corresponding instruction frequency. Assuming the remaining 60% of instructions have a CPI of 1 when there are no cache misses, we can calculate:

Average CPI with cache misses = (0.4 x 1.0) + (0.4 x 1.0 x 0.02 x 200) + (0.4 x 1.0 x 0.02 x 200) = 9.6

Average CPI with all cache hits = (0.4 x 1.0) + (0.4 x 1.0 x 0.02 x 0) + (0.4 x 1.0 x 0.02 x 0) = 1.4

The speed improvement can be calculated using the formula: Speedup = Average CPI with cache misses / Average CPI with all cache hits.

Speedup = 9.6 / 1.4 = 6.857

Therefore, the computer would be approximately 6.857 times faster if all instructions were cache hits.

Answer 2

6.6 times faster considering I-cache

Step-by-step explanation:

Given data :

CPI = 1

Data accesses ( loads and stores ) = 40% of instructions

Miss penalty = 200 clock cycles

Miss rate = 2% for I-cache , 5% for D-cache

Determine how much faster the computer will be if all instructions were Cache hits

In this condition the memory stall = 0

hence: CPU ideal time = ( Ic * CP1 + memory stall ) * clock cycle time --- ( 1 )

= ( Ic * 1 + 0 ) * clock cycle time

Note : Memory stall = Ic * ( 1 + load fraction ) * miss rate * miss penalty --- ( 2)

back to equation 1

Memory stall ( for I-cache ) = Ic * ( 1 + 40% ) * 2% * 200

= 5.6 Ic

Input value into equation 1

CPU ideal time = Ic * 1 + 5.6Ic * clock cycle time

= ( 6.6 Ic ) * clock cycle time

To determine how much faster we take the ratio of the CPU ideal time

= 6.6 Ic * clock cycle time / 1 Ic * clock cycle time

= 6.6 times faster