Question

For each of the caches described below, calculate the total number of bits needed by the cache, the data efficiency (ratio of bits per cache line used to store data and total bits per cache line), and show a representation of which bits of the memory address are used for the tag, index, block offset, and byte offset (if any). A) A 256-block direct mapped cache using 64-bit memory addresses with a block size of 1 64-bit word. Assume that memory is byte addressable (i.e. any byte in memory can be addressed and addresses do not need to be aligned to the word size). B) A 64-block direct mapped cache using 32-bit memory addresses with a block size of 16 32-bit words. Assume that memory is word addressable (i.e. memory addresses are 32-bit word aligned). C) A 512-block 4-way set associative cache using 64-bit memory addresses with a block size of 1 32-bit word. Assume that the memory is word addressable. D) A 64-block 8-way set associative cache using 32-bit memory addresses with a block size of 8 64-bit words. Assume that the memory is halfword addressable (i.e. memory addresses must align to 32-bit halfwords).

Answer 1

This detailed answer explains the total number of bits needed, data efficiency, and memory address representation for different cache configurations.

Step-by-step explanation:

A) In a 256-block direct-mapped cache with 64-bit memory addresses and a block size of 1 64-bit word, the total number of bits needed is 256 x 64 = 16,384 bits. The data efficiency is 64 bits per cache line divided by 64 bits per cache line, which is 100% efficient. The representation of the memory address is: tag (0-51 bits), index (52-75 bits), and block offset (76-127 bits).

B) For a 64-block direct-mapped cache with 32-bit memory addresses and a block size of 16 32-bit words, the total number of bits needed is 64 x 16 x 32 = 32,768 bits. The data efficiency is 16 x 32 bits per cache line divided by 32 x 32 bits per cache line, which is 50% efficient. The representation of the memory address is: tag (0-30 bits), index (31-37 bits), and block offset (38-63 bits).

C) In a 512-block 4-way set associative cache with 64-bit memory addresses and a block size of 1 32-bit word, the total number of bits needed is 512 x 4 x 64 = 131,072 bits. The data efficiency is 32 bits per cache line divided by 64 bits per cache line, which is 50% efficient. The representation of the memory address is: tag (0-51 bits), index (52-65 bits), and block offset (66-127 bits).

D) For a 64-block 8-way set associative cache with 32-bit memory addresses and a block size of 8 64-bit words, the total number of bits needed is 64 x 8 x 64 = 32,768 bits. The data efficiency is 8 x 64 bits per cache line divided by 64 x 64 bits per cache line, which is 12.5% efficient. The representation of the memory address is: tag (0-23 bits), index (24-29 bits), block offset (30-57 bits), and byte offset (58-63 bits).