1. Write about Pipeline conflicts. 2. Derive speedup achieved by a pipeline unit over a non-pipeline unit. 3. What are the pipeline conflicts that cause the instruction pipeline to deviate from? 4. Illustrate with an example an instruction pipeline.
5. Write about delayed branch. 6. Explain in detail about status bit conditions with example? 7. What is an instruction cycle and write the phases of Instruction cycle? 8. With a neat schematic, explain the steps involved in fetch and decode phases using register transfer instructions. 9. Elaborate the steps involved in execution of Memory-Reference instructions with its timing signals. 10. Using the register transfer notations, explain the Memory-Reference instructions with examples 11. Write about Interrupt and its types?
12. Write about pipelining and its importance in high speed applications. 13. Demonstrate the pipeline organization for following example Ai*Bi+Ci for i=1,2,3,...... 14. Illustrate the behavior of a pipeline using space-time diagram. 15. A non-pipeline system takes 50ns to process a task. The same task can be processed in a six segment pipeline with a clock of 10 ns. Determine speedup ratio of the pipeline for 100 tasks.
16. With examples, Explain four segment CPU pipeline and Timing of instruction pipeline. 17. Elaborate the major difficulties that cause the instruction pipeline to deviate from its normal operation.