Answer:
Let's start with the initial state of the register with the content 1101:
Q3 Q2 Q1 Q0
----------------------
INIT: 1 1 0 1
Next, we need to shift the register six times to the right with the serial input being 101101. Since we're using a rising edge trigger flip flop, we'll show the state of the register after each clock cycle.
Q3 Q2 Q1 Q0
----------------
INIT: 1 1 0 1
CLK 1: 1 1 1 0 (serial input = 1, Q0 = 1)
CLK 2: 0 1 1 1 (serial input = 0, Q0 = 0)
CLK 3: 1 0 1 1 (serial input = 1, Q0 = 1)
CLK 4: 1 1 0 1 (serial input = 1, Q0 = 1)
CLK 5: 0 1 1 0 (serial input = 0, Q0 = 0)
CLK 6: 1Based on the previous state, at CLK 6 we would have shifted the register to the right again, but there is no more serial input to shift in. Therefore, the final state of the register would be:
Q3 Q2 Q1 Q0
----------------
FINAL: 0 1 0 1
And here's the complete time diagram showing the state of the register after each clock cycle:
________ ________ ________ ________ ________ ________ ________
CLK: | || || || || || || ||
1 2 3 4 5 6 7
________ ________ ________ ________ ________ ________
SER: | 1 || 0 || 1 || 1 || 0 || 1 || 0 ||
________ ________ ________ ________ ________ ________
Q3: | 1 || 1 || 0 || 1 || 1 || 0 || 1 ||
Q2: | 1 || 1 || 1 || 0 || 1 || 1 || 0 ||
Q1: | 0 || 1 || 0 || 1 || 1 || 0 || 1 ||
Q0: | 1 || 0 || 1 || 1 || 0 || 1 || 0 ||
Note that the `X` in the SER line at the end indicates that there is no more serial input to shift in.
Hope this helps!