Question

Consider executing the following code on the pipelined datapath that we discussed in class.

During the 7th cycle, which register(s) are being read and which register(s) will be written (using the register file)?
sub $t5, $t2, $t3
add $t4, $t9, $t1
sub $t1, $t9, $t3
add $t7, $t8, $t6
lw $t6, 16($t7)
add $t2, $t9, $t3

Answer 1

Based on the given code and assuming a 5-stage pipelined datapath with stages Fetch (F), Decode (D), Execute (E), Memory (M), and Write-back (WB), the following register operations will take place during the 7th cycle:

During the 7th cycle:

Register Read: $t2, $t3, $t9, and $t8 will be read in the Decode stage (D) for the instructions sub $t5, $t2, $t3, add $t4, $t9, $t1, add $t2, $t9, $t3, and add $t7, $t8, $t6, respectively.
Register Write: No register write operation will take place during the 7th cycle as there are no instructions that update register values in the Write-back stage (WB).
Note: The instruction lw $t6, 16($t7) will be executed in the Memory stage (M), and it involves reading the value from memory and updating the register $t6. However, the result will not be written back to the register file during the 7th cycle, as the Write-back stage (WB) comes after the Memory stage (M) in the pipeline. So, the register write operation for this instruction will happen in a later cycle.