Question

3)(scan design) suppose that your chip has 100,000 gates and 2,000 flip flops. acombinational atpg program produced 500 vectors to fully test the logic. a single scanchain design will require about 106 clock cycles for testing. (a)find the scan test length including the scan register test if 20 scan chains areimplemented. (b)given that the circuit has 20 primary input and 20 primary output data pins, and onlyone extra pin can be added for test (test control tc) pi, how much more gate overhead willbe needed for the new design? assume the cost of normal data flip flop is 10 gates and the mux is 4 gates. hint: the gate overhead

Answer 1

Answer: a) To find the scan test length including the scan register test if 20 scan chains are implemented, we can use the formula:

Step-by-step explanation:

Scan Test Length = (Number of Clock Cycles * Number of Scan Chains) + (Number of Vectors * Number of Scan Chains)

Plugging in the given values, we get:

Scan Test Length = (106 * 20) + (500 * 20)

= 2,120 + 10,000

= 12,120 clock cycles

Therefore, the scan test length including the scan register test if 20 scan chains are implemented is 12,120 clock cycles.

(b) To add a test control (TC) pin, we need to add a multiplexer to the design, which selects between the normal data input and the test control input for each flip flop. The gate overhead for the multiplexer is 4 gates per flip flop. Additionally, we need to add a test control input buffer, which introduces an overhead of 10 gates.

So, the total gate overhead for adding the test control pin is:

Gate Overhead = (Number of Flip Flops * 4) + 10

= (2,000 * 4) + 10

= 8,010 gates

Therefore, we need an additional 8,010 gates for the new design with the test control pin.

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