Final answer:
The upper and lower control chart limits for computer chips, with a past defect rate of 1.1% and a sample size of 1,000, are approximately 14 and 8 defects respectively, when using a z-score of 3.
Step-by-step explanation:
To determine the upper and lower control chart limits for computer chips with a past defect rate of 1.1%, a sample size of 1,000, and using a z-score of 3, we need to employ quality control methodologies. The control limits are defined using the mean of the process and the process standard deviation, which in a quality control context is often estimated by the standard error when dealing with proportions.
The mean (proportion defective) is calculated as 1.1% of the sample size, which is 0.011 × 1,000 = 11 defects. The standard error (SE) for a proportion is determined by the formula SE = sqrt[(p×(1-p))/n], where p is the proportion of defects and n is the sample size.
Plugging in our values we get SE = sqrt[(0.011×(1-0.011))/1,000]
= sqrt[(0.011× 0.989)/1,000]
= sqrt[0.010879/1,000]
= 0.00104.
Using the z-score of 3, we calculate the control limits as follows:
- Upper Control Limit (UCL) = mean + (z × SE) = 11 + (3 × 0.00104 × 1,000) = 11 + 3.12 = 14.12
- Lower Control Limit (LCL) = mean - (z × SE) = 11 - (3 × 0.00104 × 1,000) = 11 - 3.12 = 7.88
Therefore, the upper and lower control chart limits would be approximately 14 and 8 defects, respectively. Any observation outside these limits would suggest that the process is out of control and requires investigation.