Question

Consider a pipelined processor with just one level of cache. Assume that in the absence of memory delays, the baseline CPI of this processor is 2. Now assume that the percentage of memory instructions in a typical program executed on this CPU is 50% and the memory access latency is 150 cycles. Assuming that the I-cache delays are already accounted for in the baseline CPI, consider the following two alternatives for the D-cache design:

Alternative 1: A small D-cache with a hit rate of 94% and a hit access time of 1 cycle (assume that no additional cycles on top of the baseline CPI are added to the execution on a cache hit in this case).
Alter tive 2: A larger D-cache with a hit rate of 98% and the hit access time of 2 cycles (assume that every memory instruction that hits into the cache adds one additional cycle on top of the baseline CPI).
Estimate the CPI metric for both of these designs and determine which of these two designs provides better performance. Explain your answers

Answer 1

To estimate the CPI metric for each cache design, calculate the average memory access time (AMAT) for each alternative. Alternative 2 provides better performance with a lower CPI.

Step-by-step explanation:

To estimate the CPI metric for each cache design, we need to calculate the average memory access time (AMAT) for each alternative. For Alternative 1, the AMAT can be calculated as: (Hit Rate * Hit Access Time) + (Miss Rate * Miss Penalty). Assuming the miss penalty is 150 cycles and the miss rate is (1 - hit rate), the AMAT for Alternative 1 would be (0.94 * 1) + (0.06 * 150) = 9.24 cycles.

For Alternative 2, the AMAT can be calculated as: (Hit Rate * Hit Access Time) + (Miss Rate * Miss Penalty). Assuming the miss penalty is 150 cycles and the miss rate is (1 - hit rate), the AMAT for Alternative 2 would be (0.98 * 2) + (0.02 * 151) = 4.98 cycles.

Now, to estimate the CPI metric for each design, we can use the formula: CPI = Baseline CPI + (Percentage of Memory Instructions * Memory CPI), where Memory CPI = AMAT. For Alternative 1, the CPI would be 2 + (0.5 * 9.24) = 6.62. For Alternative 2, the CPI would be 2 + (0.5 * 4.98) = 4.99.

Therefore, Alternative 2 provides better performance as it has a lower CPI, indicating faster execution on average.

The calculations reveal that Alternative 1 has a CPI of 6.97, while Alternative 2 has a CPI of 4.48. Therefore, Alternative 2 provides better performance with a lower CPI.

The student is asking about the impact of cache designs on the cycles per instruction (CPI) of a pipelined processor. We have two D-cache alternatives with different hit rates and access times. We are tasked to calculate the average CPI for each and determine which design provides better performance.

Alternative 1: Small D-cache with 94% hit rate and 1 cycle hit access time.

Alternative 2: Large D-cache with 98% hit rate and 2 cycles hit access time.

Calculations:

For Alternative 1:
CPI = Baseline CPI + (Percentage of memory instructions * (Miss rate * Miss penalty + Hit rate * Hit time))
CPI = 2 + (0.5 * ((0.06 * 150) + (0.94 * 1)))
CPI = 2 + (0.5 * (9 + 0.94))
CPI = 2 + (0.5 * 9.94)
CPI = 2 + 4.97
CPI = 6.97

For Alternative 2:
CPI = Baseline CPI + (Percentage of memory instructions * (Miss rate * Miss penalty)) + (Hit rate * Hit time)
CPI = 2 + (0.5 * (0.02 * 150)) + (0.98 * 1)
CPI = 2 + (0.5 * 3) + 0.98
CPI = 2 + 1.5 + 0.98
CPI = 4.48

Comparing both, Alternative 2 has a lower CPI, indicating better performance.