Question

1. [20 marks] a program has an 8-instruction loop that is executed many times. there is one branch instruction (the last instruction) whose target is the first instruction of the loop at memory address 3a5c70. the first loop instruction loads a different 32-bit integer in each iteration. it is the only load instruction. the first integer loaded is at memory address 4b6d60. loaded integers are adjacent, and are loaded in increasing memory-address order. the size of an instruction is 32 bits. a unified, i.e., a combination i-cache/d-cache, direct-mapped cache has 16-byte lines and 16 frames. determine the number of cache misses in the first 16 iterations. a) how many cache misses are there in the first four iterations? b) how many cache misses are there in the second four iterations? c) how many cache misses are there in the third four iterations? d) how many cache misses are there in the fourth four iterations?

Answer 1

To determine the number of cache misses in the first 16 iterations, calculate the memory addresses accessed by load instructions and check if they are in the cache. In each set of four iterations, there are 4 cache misses as the memory addresses are not initially in the cache.

Step-by-step explanation:

To determine the number of cache misses in the first 16 iterations, we need to calculate the memory address each load instruction accesses and check if it's already in the cache or not.

Given that the cache has 16-byte lines and 16 frames, we can calculate the memory addresses of the load instructions for each iteration. If the memory address is not already in the cache, it will result in a cache miss.

a) In the first four iterations, the memory addresses accessed by the load instructions are 4b6d60, 4b6d64, 4b6d68, and 4b6d6c. As these addresses are not in the cache initially since it is the first iteration, there will be 4 cache misses.

b) In the second four iterations, the memory addresses accessed by the load instructions are still not in the cache, resulting in 4 cache misses.

c) In the third four iterations, the memory addresses accessed by the load instructions are not in the cache, resulting in 4 cache misses.

d) In the fourth four iterations, the memory addresses accessed by the load instructions are not in the cache, resulting in 4 cache misses.