Question

a 256 mb dram chip is organized as a 32m x 8 memory externally and as a16k x 16k array internally. each row must be refreshed at least once every 50 ms to forestall data loss; refreshing a row takes 100 ns. what fraction of the total memory bandwidth is lost to refresh cycles?

Answer 1

About 3.2% of the total memory bandwidth of the DRAM chip is lost to refresh cycles, which equates to the time needed to refresh all the rows in relation to the total time available.

Step-by-step explanation:

The correct answer is option memory bandwidth lost to refresh cycles. Each row must be refreshed at least once every 50 ms, which means there are 20,000 refresh cycles per second (1 second / 50 ms = 20).

With 16,000 rows (given by the 16k x 16k array), all rows are refreshed every 50 ms, leading to a total of 320,000,000 refresh cycles per second (16,000 rows * 20 refreshes per second).

Each refresh cycle takes 100 ns, or 0.1 µs, which means that refreshing all rows takes 32 ms (320,000,000 * 0.1 µs). The percentage of time spent refreshing per second is the refresh time divided by the total time available in a second, multiplied by 100 to get a percentage.

So, (32 ms / 1,000 ms) * 100 = 3.2%. This means that 3.2% of the total memory bandwidth is lost to refresh cycles.