Question

The pipelined RISC-V processor is running the following code snippet. Which registers are being written and

which are being read on the fifth cycle? Recall that the pipelined RISC-V processor has a Hazard Unit. You may
assume a memory system that returns the result within one cycle.
addi s1, zero, 11 # s1 = 11
lw s2, 25(s0) # s2 = memory[s0+25]
add s3, s3, s4 # s3 = s3 + s4
or s4, s1, s2 # s4 = s1 | s2
lw s5, 16(s2) # s5 = memory[s2+16]

Answer 1

In the pipelined RISC-V processor, registers s3 and s4 are being written in the fifth cycle, while registers s3, s4, s1, and s2 are being read.

Step-by-step explanation:

RISC-V is an open standard instruction set architecture based on established reduced instruction set computer principles.

The pipelined RISC-V processor is running the following code snippet:

1. addi s1, zero, 11 - The value 11 is being written to register s1.
2. lw s2, 25(s0) - The value from memory[s0+25] is being loaded into register s2.
3. add s3, s3, s4 - The sum of registers s3 and s4 is being written to register s3.
4. or s4, s1, s2 - The bitwise OR of registers s1 and s2 is being written to register s4.
5. lw s5, 16(s2) - The value from memory[s2+16] is being loaded into register s5.

In the fifth cycle, the registers being written are s3 and s4, while the registers being read are s3, s4, s1, and s2.