Question

Recall that each MIPS instruction opcode is 6 bits. Use 2 hex digits to show the opcode for each of the instructions listed below and indicate whether the instruction is executed by the CPU, CP0 or CP1.

a. addiu
b, lwc1
c. tc1
d. cvt.s.w
e. cvt.w.s
f. mfc1
g. sw
h. bc1t

Answer 1

MIPS instruction opcodes are 6-bit values, represented using two hexadecimal digits. These opcodes indicate tasks for CPU or its coprocessors. Some example opcodes include 'addiu' (09), 'lwc1' (31), 'cvt.s.w' (split between 10 and 20), 'cvt.w.s' (split between 11 and 24), 'mfc1' (00), 'sw' (2B), and 'bc1t' (part of 11).

Step-by-step explanation:

The opcodes for MIPS instructions represent the operation that the CPU, CP0 (Coprocessor 0), or CP1 (Coprocessor 1) needs to perform. Opcodes are formatted using hexadecimal representation. Below is a list of some MIPS opcodes for the respective instructions:

• addiu (CPU): 09
• lwc1 (CP1): 31
• tc1 (unspecified, possibly a typo): opcode not available
• cvt.s.w (CP1): The opcode part of the instruction format is actually split between the COP1 prefix (10) and the function field (20)
• cvt.w.s (CP1): Similar to cvt.s.w, it's represented by COP1 prefix (11) and function field (24)
• mfc1 (CP1): 00 (as part of the COP1 opcode)
• sw (CPU): 2B
• bc1t (CP1): 11 (as part of the COP1 opcode, with additional fields to indicate the 't' condition)

It is important to note that cvt.s.w and cvt.w.s involve both an opcode and a function code and are part of the COP1 instruction set, which means that they are executed by Coprocessor 1 (used for floating-point operations).