Question

A processor executes every ALU instruction in 1 cycle, load and store instructions in 2 cycles, and branches in 3 cycles. If 45% of instructions are ALU instructions, 30% are load/store instructions, and all remaining instructions are branches, what is the resulting CPI (cycles per instruction) of that machine? What is the resulting speedup if the latency of branches is reduced by an architectural change to one cycle?

Answer 1

The CPI of the processor is calculated to be 1.85, considering the cycles consumed by each type of instruction weighted by their occurrence frequency. By reducing the branch instruction latency to one cycle, the CPI is lowered to 1.45, resulting in a speedup of approximately 1.28 times.

Step-by-step explanation:

The subject of this question is the calculation of the average cycles per instruction (CPI) for a processor and the performance improvement (speedup) after an architectural change. To calculate the CPI, we consider the execution cycles for each type of instruction and their corresponding frequency of occurrence. The CPI is calculated as follows:

The resulting CPI is obtained by summing these products, which comes out to:

CPI = 0.45 × 1 + 0.30 × 2 + 0.25 × 3 = 1.85

To calculate the speedup when the branch latency is reduced to one cycle, we recalculate the CPI with the new cycle count for branches:

New CPI = 0.45 × 1 + 0.30 × 2 + 0.25 × 1 = 1.45

Speedup is then calculated as the original CPI divided by the new CPI:

Speedup = Original CPI / New CPI = 1.85 / 1.45 ≈ 1.28

Thus, the speedup achieved with the architectural change is approximately 1.28 times.