Question

HE CPU AND MEMORY (Chapter 7) If the memory register for a particular computer is 32 bits wide, how much memory can this computer support? Show the steps of the CPU fetch–execute cycle (micro operations) for the following instructions in the Little Man instruction set: SUBTRACT, IN, COFFEE BREAK, BRANCH ON CONDITION Show the steps of the CPU fetch–execute cycle (micro operations) for an instruction that produces the 2’s complement of the number in accumulator A (calculator). (8 marks) Assume that SP is the stack pointer regiester, a special purpose register that always refers to the top of the stack. PUSH is an instruction that pushes the address of the next instruction into the top of the stack. Show the steps of the CPU fetch–execute cycle (micro operations) for the PUSH instruction. Part B: CPU AND MEMORY: DESIGN, ENHANCEMENT, AND IMPLEMENTATION (Chapter 8) Consider a CPU that implements a single instruction fetch–decode–execute–write- back pipeline for scalar processing. The execution unit of this pipeline assumes that the execution stage requires one step. Describe, and show in diagram form, what happens when an instruction that requires one execution step follows one that requires four execution steps. Some systems use a branch prediction method known as static branch prediction, so called because the prediction is made on the basis of the instruction, without regard to history. One possible scenario would have the system predict that all conditional backward branches are taken and all forward conditional branches are not taken. Recall your experience with programming in the Little Man Computer language. Would this algorithm be effective? Why or why not? What aspects of normal programming, in any programming language, support your conclusion? Suppose we are trying to determine the speed of a computer that executes the Little Man instruction set. The LOAD and STORE instructions each make up about 25% of the instructions in a typical program; ADD, SUBTRACT, IN, and OUT take 10% each. The various branches each take about 5%. The HALT instruction is almost never used (a maximum of once each program, of course!). Determine the average number of instructions executed each second if the clock ticks at 100 MHz. Now suppose that the CPU is pipelined, so that each instruction is fetched while another instruction is executing. (You may also neglect the time required to refill the pipeline during branches and at the start of program execution.) What is the average number of instructions that can be executed each second with the same clock in this case? Consider a cache memory that provides three hundred 16-byte blocks. Now consider that you are processing all the data in a two-dimensional array of, say, four hundred rows by four hundred columns, using a pair of nested loops.Assume that the program stores the array column by column. You can write your program to nest the loops in either direction, that is, process row by row or column by column. Explain which way you would choose to process the data? Why?

Answer 1

A 32-bit memory register can address up to 4GB of memory. The fetch-execute cycle varies for different instructions within the Little Man Computer instruction set. The CPU's speed of executing LMC instructions and its pipelined configuration, as well as cache optimization techniques when processing two-dimensional arrays, can significantly impact computer performance.

Step-by-step explanation:

The memory register width of a computer dictates the amount of memory it can address. A 32-bit register can support a memory capacity of 4GB, since 2^32 is 4,294,967,296 addresses and each address references a single byte. The fetch-execute cycle for the Little Man Computer (LMC) includes several micro-operations such as fetching the instruction, decoding it, executing the operation, and storing results.

The fetch-execute cycle for instructions like SUBTRACT and IN consists of fetching the instruction from memory, decoding it to understand the operation required, executing it by performing the operation with the accumulator, and writing back the result. For PUSH, the cycle would also involve manipulating the stack pointer to store the address on the top of the stack.

In CPUs with a fetch-decode-execute-write-back pipeline, a scalar processing instruction that takes four steps would introduce pipeline stalls if followed by an instruction requiring only one step. Static branch prediction might not always be effective with the LMC instruction set, as conditional branches depend heavily on runtime conditions that static prediction cannot anticipate.

Answer 2

The memory capacity of a computer with a 32-bit wide memory register is 4 gigabytes. The CPU fetch-execute cycle consists of fetch, decode, execute, and update steps. The PUSH instruction involves fetching the instruction, decoding it, updating the stack pointer register, pushing the address of the next instruction onto the stack, and updating the program counter.

Step-by-step explanation:

Memory Capacity

The memory capacity of a computer with a 32-bit wide memory register can be calculated using the formula 2 raised to the power of the number of bits. In this case, it would be 2^32, which equals 4,294,967,296 bits or 4 gigabytes (since 8 bits make up 1 byte).

CPU Fetch-Execute Cycle

The CPU fetch-execute cycle consists of several micro operations:

Fetch: The CPU fetches the instruction from memory.

Decode: The CPU decodes the instruction to determine what operation to perform.

Execute: The CPU performs the operation indicated by the instruction.

Update: The CPU updates the program counter to the address of the next instruction.

The steps for specific instructions, such as SUBTRACT, IN, COFFEE BREAK, BRANCH ON CONDITION, or the 2’s complement of the number in accumulator A, would depend on the specific implementation of the Little Man instruction set.

PUSH Instruction

The steps for the PUSH instruction in the CPU fetch-execute cycle are:

Fetch the PUSH instruction from memory.

Decode the instruction to determine the operation and operand.

Update the stack pointer register (SP) to point to the top of the stack.

Push the address of the next instruction onto the stack.

Update the program counter to the address of the next instruction.

Design and Pipelining

When an instruction that requires one execution step follows one that requires four execution steps in a single instruction fetch-decode-execute-write-back pipeline, the execution of the first instruction would have to wait until the execution stage of the second instruction completes. This can lead to a pipeline stall, resulting in decreased efficiency.

Static branch prediction, which predicts all conditional backward branches as taken and all forward conditional branches as not taken, would not be effective in the Little Man instruction set because the behavior of conditional branches cannot be accurately predicted based solely on the instruction itself. The outcome of conditional branches in the Little Man instruction set depends on the values stored in memory or accumulator registers, which cannot be determined without executing the instructions.

Clock Speed and Pipelining

If the clock ticks at 100 MHz and the proportion of instructions in a typical program is given, the average number of instructions executed per second can be calculated as follows:

Calculate the average number of instructions executed per second without pipelining: (Clock Speed / Instruction Execution Time) * Proportion of Instructions

Calculate the average number of instructions executed per second with pipelining: (Clock Speed / Pipeline Efficiency) * Proportion of Instructions

Data Processing

If a cache memory provides three hundred 16-byte blocks and a two-dimensional array of 400 rows by 400 columns is being processed using nested loops, it would be more efficient to process the data row by row. This is because accessing memory in a contiguous manner (row by row) allows for better utilization of cache memory, reducing cache misses and improving performance.