Final answer:
The minimum page size in the system detailing physical and virtual addresses should be at least equal to the cache line size, which is 128 bytes, to allow for efficient TLB and cache operation where one TLB entry corresponds to one cache line.
Step-by-step explanation:
The minimum page size in a system with physically-addressed caches using 36-bit virtual addresses, 32-bit physical addresses, and a cache line size of 128 bytes, designed to allow for the overlap of the TLB (Translation Lookaside Buffer) access and the cache access, should be at least the size of the cache line, which is 128 bytes. This is because the TLB stores the address translation from virtual to physical, and if the page size is smaller than the cache line size, you could have multiple TLB entries for a single cache line. To ensure efficient TLB and cache operation with a single TLB entry matching a single cache line, the page size should be no less than the size of a cache line, thus maintaining consistency between memory page and cache line.
To determine the minimum page size that would allow for the overlap of the TLB access and the cache access, we need to consider the number of cache lines and the number of TLB entries. In this case, the cache has a total size of 64 kbytes, which means it can hold 64,000 / 128 = 500 cache lines. The TLB, on the other hand, can translate 2^32 physical addresses to their corresponding 36-bit virtual addresses. Therefore, it can have a maximum of 2^32 entries. To allow for overlap, the minimum page size should be such that the number of TLB entries is greater than or equal to the number of cache lines. So the minimum page size can be calculated as 2^32 / 500 = 8,589,934.59 bytes, or approximately 8.59 MB.