Question

Non-pipelined processor, 5 clock cycles to complete an instruction with 2.5 GHz processor frequency. Now we are making a 5-stage pipeline, 2 GHz (due to pipeline overheads) processor operating frequency. The program we wish to run has 30% memory, 60% ALU, and the rest of the branch. 5% memory instructions cause stalls of 50 clock cycles each due to some reason, and 50% branch instructions cause stalls of 2. No stall for ALU, speed up?

A) 1.25x
B) 1.50x
C) 1.75x
D) 2.00x

Answer 1

The 5-stage pipelined processor experiences a slow down rather than a speed up, with a calculated performance of approximately 0.68 times that of the non-pipelined processor due to the impact of memory and branch stalls within the pipeline.

Step-by-step explanation:

To calculate the speed up of a 5-stage pipeline processor over a non-pipelined processor, we need to consider the initial clock cycles, frequency, pipeline overheads, and the nature of the program to be run.

The non-pipelined processor operates at 2.5 GHz and takes 5 clock cycles to complete an instruction, which results in an execution time of 2 ns per instruction. The pipeline processor operates at a reduced frequency of 2 GHz to account for pipeline overheads, resulting in a base execution time of 0.5 ns per instruction stage, or 2.5 ns in total since there are 5 stages.However, the performance is affected by stalls caused by memory and branch instructions. With 30% of the instructions being memory operations, 5% of these cause a 50-cycle stall each. Branch instructions constitute 10% of the program, half of which cause a 2-cycle stall.

To get the effective cycle time for the pipelined processor, we add the stalls due to memory and branch stalls to the base cycle count of the program. For memory instructions: 30% of instructions are memory-related, 5% of these have stall cycles, hence 0.3 * 0.05 * 50 = 0.75 extra cycles on average per instruction. For branch instructions: 10% of instructions are branch-related, 50% of these have stall cycles, hence 0.1 * 0.5 * 2 = 0.1 extra cycles on average per instruction. This gives us a total average of 0.85 extra cycles per instruction.The total effective cycle time for the pipelined processor becomes 5 + 0.85 = 5.85 cycles per instruction. Given the 2 GHz pipeline processor frequency, the execution time is 5.85 * 0.5 ns = 2.925 ns. Now, to find the speed up, we take the non-pipelined execution time divided by the pipelined execution time: 2 ns / 2.925 ns = ~0.68x, which means the pipeline actually slows down the execution rather than speeding it up, hence none of the provided options A) 1.25x, B) 1.50x, C) 1.75x, or D) 2.00x are correct under the given conditions.