Question

In older processors such as the intel pentium or alpha 21264, the second level of cache was external (located on a different chip) from the main processor and the first level cache. while this allowed for large second level caches, the latency to access the cache was much higher, and the bandwidth was typically lower because the second level cache ran at a lower frequency. assume a 512 kib off-chip second level cache has a global miss rate of 4%. if each additional 512 kib of cache lowered global miss rates by 0.7%, and the cache had a total access time of 50 cycles, how big would the cache have to be to match the performance of the second level direct-mapped cache listed above? of the eight-way set associative cache?

a. Base CPI, no memory stalls , 2.0
b. Processor speed, 3 GHz
c. Main memory access time, 90 ns
d. First-level cache miss rate per instruction, 6.5 %
e. Second-level cache, direct-mapped speed, 18
f. Global miss rate with second-level cache, direct-mapped, 3.5 %
g. cycles Second-level cache, eight-ways et associative speed, 30
h. Global miss rate with second-level cache, eight-way set associative, 2.5%

Answer 1

The cache must be at least 512 KiB to match the performance of a direct-mapped cache with a miss rate of 3.5%. To match an eight-way set associative cache with a 2.5% miss rate, the cache size needs to be expanded to 1.5 MiB.

Step-by-step explanation:

The question revolves around the performance implications of cache sizes on older processors, specifically focused on the miss rate improvements and the total access time when increasing the cache size. If the base second-level cache has a 4% global miss rate and each additional 512 KiB decreases this miss rate by 0.7%, we need to find out how large the cache must be to match a direct-mapped cache with a 3.5% global miss rate.

To match a 3.5% miss rate starting from a 4% base miss rate, we continue to decrement by 0.7% for each additional 512 KiB. After the first 512 KiB (4% - 0.7% = 3.3%), the next 512 KiB would reduce the miss rate to 2.6%, then to 1.9%, and so forth. To get to a miss rate equal to or lower than 3.5%, no additional cache is required because after the first upgrade, the new miss rate is already below 3.5%.

Now, to match an eight-way set associative cache with a 2.5% miss rate, more additions are required. We would need more than two increments to go below the 2.5% threshold (3.3% after the first increment and 2.6% after the second), meaning that at least one more 512 KiB block is required to reach a miss rate lower than 2.5%, putting the total cache size at 1.5 MiB minimum.