Final answer:
The 'sw t1, 32(t2)' instruction is a Store Word I-type instruction in MIPS assembly. The hexadecimal representation for this is 0xAD09 0020 after considering the opcode for 'sw', the register numbers for t1 and t2, and the offset value of 32 in hexadecimal. None of the provided options are correct.
Step-by-step explanation:
The instruction sw t1, 32(t2) is a Store Word type instruction in MIPS assembly language. This instruction is used to store a 32-bit word from register t1 into the memory address computed by adding a 32-byte offset to the address contained in register t2. To construct the hexadecimal representation, we look into the MIPS instruction format and encoding.
The Store Word instruction follows the I-type (Immediate) format, with an opcode for Store Word, the base register (t2), the target register (t1), and the 16-bit immediate (the offset).
A MIPS 'Store Word' (sw) instruction has the following fields:
opcode (6 bits) for sw is 2B,
source register (rs, 5 bits) is t2,
target register (rt, 5 bits) is t1,
and the immediate (16 bits), which is the offset 32 or 0x0020 in hexadecimal.
Considering the MIPS registers convention, where $t1 corresponds to register number 9 and $t2 corresponds to register number 10, the full instruction encoding in hexadecimal becomes 0xAD09 0020 after translating each field into its hexadecimal representation and combining them.