Final answer:
To create a minimal SOP circuit for the given function, K-map techniques are utilized to simplify the boolean expression before logic network design. The network is implemented using NAND gates, with cost computed based on gate count and inputs.
Step-by-step explanation:
To design a minimal SOP circuit using a Karnaugh map (K-map) for the function f(x1,x2,x3,x4)=Π[M(2,3,6,9,11,12,13,14,15)], we begin by identifying the min-terms where the function is zero, which are given by the indices in the product term. To simplify the circuit using only NAND gates, we plot the zeros on the K-map and group them to simplify the expression to its minimum SOP form. The resulting simplified boolean expression can then be implemented using NAND gates, by realizing that a NAND gate can be used both as an inverter (by shorting its inputs) and as a standard NAND operation. The groups on the K-map will guide us in creating an equivalent NAND-only network.
After diagramming this minimal SOP expression with NAND gates, we can compute the cost of the NAND logic network by counting the number of individual NAND gates and the number of inputs to each gate (assuming that the cost is proportional to the number of inputs). Typically, each gate contributes 1 to the cost and each additional input beyond 2 inputs adds to the cost of that particular gate. At the end of the computation, we have our total cost.