Question

Given F=A'B'C'. Assume transistor widths chosen to achieve effective rise and fall resistance equal to that of a unit inverter. What will be the falling propagation delay if the function is modified to F= A'B'C'DD'?

a) 15hRC
b) 4RC
c) Remains the same
d) None

a) Estimate the rising propagation delay.
a) 15hRC
b) 9RC
c) 4RC
d) None

b) If an LED is connected to the output, which condition will turn it on?
a) A=0, B=0, C=1
b) A=0, B=1, C=0
c) A=1, B=1, C=1
d) A=0, B=0, C=0

c) For which condition will the falling delay be minimum?
a) A=1, B=0, C=1
b) A=0, B=1, C=0
c) A=1, B=1, C=0
d) A=1, B=1, C=1

d) Calculate the total source capacitance for the pull-down network.
a) 7C
b) 3C
c) 6C
d) 0

e) How many transistors are required to design the CMOS equivalent ˚uit for the given boolean function F?
a) 6
b) 3
c) 4
d) 2

f) What will be the rising propagation delay if the function is modified to F= A'B'C'DD'?
a) 15hRC
b) 4RC
c) Remains the same
d) None

g) Calculate the total gate capacitance for each input.
a) 4C
b) 3C
c) 6C
d) 7C

Answer 1

The falling propagation delay for the modified function F= A'B'C'DD' will be longer compared to the original function F= A'B'C'.

Step-by-step explanation:

In order to calculate the falling propagation delay for the modified function F= A'B'C'DD', we need to determine the effective rise and fall resistance. Since the transistor widths are chosen to achieve the same effective rise and fall resistance as a unit inverter, we can assume that the effective resistance is equal to 1 unit. The falling propagation delay can be calculated using the formula t = RC, where R is the effective resistance and C is the total source capacitance. As the function is modified to include an additional term D, the total source capacitance will increase. However, the effective resistance remains the same. Therefore, the falling propagation delay for the modified function F= A'B'C'DD' will be longer compared to the original function F= A'B'C'.