Question

Objectives

1) Design a BCD to 7-seg display decoder USING A ROM.
2) Simulate and implement the design using ModelSim and Intel Quartus Prime tools.

Equipment
ODE-10 lite FPGA development board.

Procedure:
1) Refer to the lecture notes for operation of ROM.
2) Using the Quartus Prime Lite and the ModelSim tools:
a. Write behavioral VHDL code for a ROM that decoded a BCD input to a 7-seg display
b. Synthesis you design.
c. Simulate your design and verify its operation.
d. Refer to the user manual of the FPGA board for FPGA pin locations connected to seven-segment display. Complete the pin assignment to connect the ROM inputs inputs to switches and outputs to a seven-segment display.
e. Perform FPGA implementation to generate bitstream.
f. Configure FPGA with bitstream and verify the design.

Answer 1

This question involves designing a BCD to 7-segment display decoder using a ROM and implementing it using ModelSim and Intel Quartus Prime tools. The design process includes writing behavioral VHDL code, synthesizing and simulating the design, and performing FPGA implementation.

Step-by-step explanation:

The objective of this question is to design a BCD to 7-segment display decoder using a ROM and implement the design using ModelSim and Intel Quartus Prime tools. The first step is to write behavioral VHDL code for a ROM that decodes a BCD input to a 7-segment display. The design is then synthesized and simulated to verify its operation.

Next, the FPGA pin locations connected to the seven-segment display should be determined by referring to the user manual of the FPGA board. Complete the pin assignment to connect the ROM inputs to switches and outputs to the seven-segment display.

Finally, FPGA implementation is performed to generate a bitstream, which can be used to configure the FPGA and verify the design.