Question

Using the following requirements calculate the following:

1) Feed voltages must be symmetrical, ie Vee = −VCC.
2) Av voltage gain = VO /VI in small signals should be AV = 100+50n1.
3) The polarization voltage in the collector must be approximately VCC /4.
4) Q1 polarization current should be IP = 5 (n2 +1) A.
5) The polarization voltage in the sender should be 3Vee /4.
6) All 3 transistors must be in the active region.

a) Calculate the lowest VC voltage possible for which the Q1 transistor is still in active mode.

Answer 1

The lowest VC voltage possible for the Q1 transistor to remain in active mode is calculated using the relation VC > VE + VBE, with VE being -3VCC/4 and VBE typically around 0.7V for silicon transistors.

Step-by-step explanation:

To calculate the lowest VC voltage for which the Q1 transistor remains in active mode, we need to ensure that the collector-emitter voltage (VCE) is greater than the base-emitter voltage (VBE). For silicon transistors, VBE is typically around 0.7V when the transistor is conducting. Since the polarization voltage in the collector is specified to be approximately VCC/4, we'll call this voltage VCCOL. Additionally, the question states that the polarization voltage in the sender (emitter) should be 3Vee/4, and since Vee is equal to -VCC, we can calculate the emitter voltage VE as -3VCC/4.

To keep Q1 in active mode, the voltage across VCE (VCE = VC - VE) must be greater than VBE. Therefore, the lowest VC is when VCE is just above 0.7V. Given VE as -3VCC/4, and considering VBE of 0.7V, the lowest VC that keeps Q1 in active mode can be calculated using the following relation:

VC > VE + VBE
VC > -3VCC/4 + 0.7V
This gives us a formula to find VC based on the value of VCC.