Question

Design an active-high word line address decoder that takes three (3) address bits: A₂A₁A and activates one of eight word lines word0 ... word7 using a predecoder stage to minimize the number of logic gates. Your design should use three (3) inverters, four (4) NAND2, and eight (8) NOR2 gates.

Answer 1

An active-high word line address decoder for three address bits can be designed with three inverters, four NAND2 gates, and eight NOR2 gates, using a predecoder stage to generate combinations of pairs of address bits for the NOR2 gates to activate individual word lines.

Step-by-step explanation:

To design an active-high word line address decoder with a predecoder stage, we can proceed as follows using three (3) address bits: A2, A1, and A0. First, generate the complement of the address bits using three inverters. This will give us A2', A1', and A0'. Next, use a predecoder stage with four NAND2 gates to generate the four possible combinations of pairs of address bits:

• NAND2 gate for A2 and A1 giving us A2A1
• NAND2 gate for A2 and A1' giving us A2A1'
• NAND2 gate for A2' and A1 giving us A2'A1
• NAND2 gate for A2' and A1' giving us A2'A1'

Now, each word line from word0 to word7 can be activated using one of the eight NOR2 gates, combining the output of the predecoder stage with A0 or A0' properly to ensure only one line is active for each combination of address bits. For example:

• word0 = NOR2(A2'A1', A0')
• word1 = NOR2(A2'A1', A0)
• word2 = NOR2(A2'A1, A0')
• ... and so on until
• word7 = NOR2(A2A1, A0)