Question

For the following assume that values A, B, C, D, E, and F reside in memory. Also assume that instruction operation codes are represented in 8 bits, memory addresses are 64 bits, and register addresses are 6 bits.

a. For each instruction set architecture shown in Figure A.2, how many addresses, or names, appear in each instruction for the code to compute C=A+B, and what is the total code size?

Here is the example for C=A+B

Stack Accumulator Register(register-memory) Register (load-store)
Push A Load A Load R1, A Load R1, A
Push B Add B Add R3, R1, B Load R2, B
Add Store C Store R3, C Add R3, R1, R2
Pop C Store R3, C

Answer 1

The code to compute C=A+B in different instruction set architectures requires varying numbers of instructions and total code sizes.

Step-by-step explanation:

Computing C=A+B in Different Instruction Set Architectures

For the code to compute C=A+B, let's analyze each instruction set architecture shown in Figure A.2:

Stack Architecture

1. Push A
2. Push B
3. Add
4. Pop C

Total code size: 4 instructions

Accumulator Architecture

1. Load A
2. Add B
3. Store C

Total code size: 3 instructions

Register-Memory Architecture

1. Load R1, A
2. Load R1, B
3. Add R3, R1, B
4. Store R3, C

Total code size: 4 instructions

Register (Load-Store) Architecture

1. Load R1, A
2. Add R1, B
3. Store R1, C

Total code size: 3 instructions