Final answer:
The 'always block' in a flip-flop design is used to define the 'when' part of the flip-flop. Conditional statements are used to specify the conditions under which the flip-flop should change its state.
Step-by-step explanation:
In a flip-flop design, the "always block" is used in a hardware description language like Verilog or VHDL to define the behavior of the flip-flop. The 'when' part of the flip-flop design is typically defined using conditional statements in the 'always block'. These conditional statements specify the conditions under which the flip-flop should change its state.
For example, in a positive-edge triggered D flip-flop, the 'when' part of the design can be defined using an 'if' statement that checks if the clock signal is at a rising edge. If the condition is true, the flip-flop will update its output based on the input value.
By properly defining the 'when' part of the flip-flop design using the 'always block', the designer can ensure that the flip-flop operates correctly according to the desired behavior.