Question

A large microprocessor draws a total transient current of 10 A from a 3.3−V supply. The logic has a rise/fall time of 1 ns. It is desirable to limit the Vcc-to-ground noise voltage peaks to 250mV, and each decoupling capacitor has 5nH of inductance in series with it. The decoupling will be done with a multiplicity of equal-value capacitors and should be effective at all frequencies above 20MHz.

a. Draw a plot of the target impedance versus frequency.

Answer 1

The target impedance versus frequency can be plotted using the formula Z_T = sqrt(Z_S^2 + Z_P^2), where Z_S is the source impedance and Z_P is the parasitic impedance due to the decoupling capacitors. The source impedance can be approximated as the transient current divided by the voltage noise. The parasitic impedance due to the decoupling capacitors can be calculated as (2πfL)^-1, where f is the frequency and L is the inductance of the decoupling capacitors.

Step-by-step explanation:

The target impedance versus frequency can be plotted using the formula:

ZT = √(ZS2 + ZP2)

where ZS is the source impedance and ZP is the parasitic impedance due to the decoupling capacitors. In this case, the source impedance is the output impedance of the microprocessor, which can be approximated as the transient current divided by the voltage noise:

ZS = 10 A / 0.250 V = 40 Ω

The parasitic impedance due to the decoupling capacitors can be calculated as:

ZP = (2πfL)-1

where f is the frequency and L is the inductance of the decoupling capacitors. Since each decoupling capacitor has an inductance of 5nH, the total inductance can be calculated as:

L = 5nH * N

where N is the number of capacitors used for decoupling.

Plugging in the values, the target impedance can be calculated for each frequency from 20MHz to 200MHz: