Question

The data cache has a 92% hit rate and a 2-cycle hit latency,and the cache miss penalty is 124 cycles. 30% of instructions are loads and stores. the instruction cache has a hit rate of 90% with a miss penalty of 50 cycles. assume the base CPI using a perfect memory system is 1.0. Caculate the CPI of the pipeline,assuming everything else is working perfectly. assume the load never stalls a dependent instruction and assume the processor must wait for stores to finish when they miss the cache. Finally,assume the instruction cache misses and data cache musses never occurr at the same time.show your work.

1.Caculate the additional CPI due to the instruction cache stalls.

2.caculate the additional CPI due to the data cache stalls.

3.Caculate the overall CPI for the machine.​

Answer 1

would be 1.0 + 0.5 cycles + 3.48384 cycles = 4.98384 cycles

Step-by-step explanation:

1 - To calculate the additional CPI due to the instruction cache stalls, we need to consider the instruction cache hit rate and the miss penalty.

First, let's calculate the instruction cache miss rate. Since the instruction cache has a hit rate of 90%, the miss rate can be calculated as 100% - 90% = 10%.

Next, we need to calculate the average instruction cache access time. We know that the miss penalty is 50 cycles. Since the miss rate is 10%, the average instruction cache access time can be calculated as 10% * 50 cycles = 5 cycles.

To calculate the additional CPI due to instruction cache stalls, we need to multiply the average instruction cache access time by the instruction cache miss rate. In this case, it would be 5 cycles * 10% = 0.5 cycles.

Therefore, the additional CPI due to the instruction cache stalls is 0.5 cycles.

2 - To calculate the additional CPI due to the data cache stalls, we need to consider the data cache hit rate, the miss penalty, and the percentage of loads and stores.

The data cache has a hit rate of 92% and a miss penalty of 124 cycles. We also know that 30% of the instructions are loads and stores.

To calculate the average data cache access time, we need to consider both hits and misses. The average data cache access time can be calculated as (hit rate * hit latency) + (miss rate * miss penalty). The hit rate is 92% and the hit latency is 2 cycles, so (hit rate * hit latency) = 92% * 2 cycles = 1.84 cycles.

The miss rate can be calculated as 100% - hit rate = 100% - 92% = 8%. Therefore, the miss rate is 8%. The average data cache access time can now be calculated as (1.84 cycles * 92%) + (8% * 124 cycles) = 1.6928 cycles + 9.92 cycles = 11.6128 cycles.

To calculate the additional CPI due to the data cache stalls, we need to multiply the average data cache access time by the percentage of loads and stores. In this case, it would be 11.6128 cycles * 30% = 3.48384 cycles.Therefore, the additional CPI due to the data cache stalls is 3.48384 cycles.

3 - To calculate the overall CPI for the machine, we need to add the additional CPI due to instruction cache stalls and the additional CPI due to data cache stalls to the base CPI of 1.0 (assuming a perfect memory system).

The overall CPI is calculated as base CPI + additional CPI due to instruction cache stalls + additional CPI due to data cache stalls.

In this case, it would be 1.0 + 0.5 cycles + 3.48384 cycles = 4.98384 cycles.

Therefore, the overall CPI for the machine is 4.98384 cycles.