Question

Consider the following architecture. 1 cache block = 16 words. Main memory latency is the time delay for each data transfer, which = 10 memory bus clock cycles. A memory transfer time = 1 memory bus clock cycle, which is also called bandwidth time. For any memory access, it consists of latency time plus the bandwidth time. The cache miss penalty is the time to transfer one block from main memory to the cache. In addition, it takes 1 clock cycle to send the address to the main memory. Compute the miss penalty for the following configurations. Configuration (a): Requires 16 main memory accesses to retrieve a cache block and words of the block are transferred one at a time. Configuration (b): Requires 4 main memory accesses to retrieve a cache block and words of the block are transferred four at a time. Configuration (c): Requires 4 main memory accesses to retrieve a cache block and words of the block are transferred one at a time.

Answer 1

The answers are A)176 B)44 C)56.

Step-by-step explanation:

According to the information given in the question about the architecture that is used and its communication times;

For option A: The goal is to retrieve one cache block which consists of 16 words. Doing this one word at a time over a period of 16 main memory accesses and the miss penalty for this configuration is 10*16 = 160 bus clock cycles for data transfer and 1*16 = 16 bus clock cycles for memory transfer time which comes up to 176.

For option B: The goal is to retrieve one cache block which consists of 16 words. Doing this four words at a time over a period of 4 main memory accesses and the miss penalty for this configuration is 10*4 = 40 bus clock cycles for data transfer and 1*4 = 4 bus clock cycles for memory transfer which comes up to 44.

For option C: The goal is to retrieve one cache block which consists of 16 words. Doing this 4 words at a time over a period of 4 main memory accesses and the miss penalty for this configuration is 10*4 = 40 bus clock cycles for data transfer and 1*16 = 16 bus clock cycles for memory transfer since words of the block are transferred not 4 but 1 at a time which comes up to 56.

I hope this answer helps.