Question

$ A-2 ISA classes) Your task is to compare the memory efficiency of four different styles of instruction set architectures. The architecture styles are: - Accumulator-All operations occur between a single register and a memory location. - Memory-memory-All instruction addresses reference only locations. - Stack-All operations occur on top of the stack. Push and pop are the only instructions that access memory; all others remove their operands from the stack and replace them with the result. The implementation uses a hardwired stack for only the top two stack entries, which keeps the processor circuit very small and low in cost. Additional stack positions are kept in memory locations, and accesses to these stack positions require memory references, Load-store-All operations occur in registers, and register-to-register instructions have three register names per instruction. To measure memory efficiency, make the following assumptions about all four instruction sets: - All instructions are an integral number of bytes in length. - The opcode is always one byte (8 bits). - Memory accesses use direct, or absolute, addressing. - The variables A, B, C, and D are initially in memory. Figure A.2 The code sequence for C=A+B for four classes of instruction sets. Note that the Add instruction has implicit operands for stack and accumulator architectures and explicit operands for register architectures. It is assumed that A,B, and C all belong in memory and that the values of A and B cannot be destroyed. Figure A.1 shows the Add operation for each class of architecture. (a) Invent your own assembly language mnemonics (Figure A.2 provides a useful sample to generalize), and for each architecture write the best equivalent assembly language code for this high-level language code sequence:

A=B+C
B=A+C
D=A−B
​
(b) In your assembly codes for part (a), point out the following information. i. Where a value is loaded from memory after having been loaded once? ii. Where the result of one instruction is passed to another instruction as an operand? iii. Are the above events in (ii) involving the storage within the processor or in memory? (c) Assume that the given code sequence is from a small, embedded computer application that uses a 16-bit memory address and data operands. If a loadstore architecture is used, assume it has 16 general-purpose registers. For each architecture answer the following questions: i. How many instruction bytes are fetched? ii. How many bytes of data are transferred from/to memory? iii. Which architecture is most efficient as measured by total memory traffic (code+data)?

Answer 1

This response compares the memory efficiency of four different instruction set architectures (Accumulator, Memory-memory, Stack, and Load-store) by inventing assembly language mnemonics for the given code operations and analyzing memory traffic based on instruction fetches and data transfers.

Step-by-step explanation:

The task involves comparing the memory efficiency of four different instruction set architectures (ISA) — Accumulator, Memory-memory, Stack, and Load-store — using the given assumptions. We can invent mnemonics for each architecture to represent the operations required for the following code:

A=B+C;
B=A+C;
D=A-B;

Accumulator Architecture

LDA B ; Load B
ADD C ; Add C
STA A ; Store result in A
LDA A ; Load A
ADD C ; Add C
STA B ; Store result in B
LDA A ; Load A
SUB B ; Subtract B
STA D ; Store result in D

Memory-memory Architecture

LOAD A, B ; A = B
ADD A, C ; A = A + C
STORE B, A ; B = A
LOAD A, C ; A = C
ADD B, A ; B = B + A
STORE A, B ; D = A - B

Stack Architecture

PUSH B ; B onto stack
PUSH C ; C onto stack
ADD ; Add top two stack entries
POP A ; Pop result into A
PUSH A ; A onto stack
PUSH C ; C onto stack
ADD ; Add top two stack entries
POP B ; Pop result into B
PUSH A ; A onto stack
PUSH B ; B onto stack
SUB ; Subtract top two stack entries
POP D ; Pop result into D

Load-store Architecture

LOAD R1, B ; R1 = B
LOAD R2, C ; R2 = C
ADD R3, R1, R2 ; R3 = R1 + R2
STORE A, R3 ; A = R3
ADD R4, R3, R2 ; R4 = R3 + R2
STORE B, R4 ; B = R4
SUB R5, R3, R4 ; R5 = R3 - R4
STORE D, R5 ; D = R5

In these examples, the location from which values are loaded after being loaded once, and the result of one instruction passed to another as an operand can be easily identified. These events take place either within the processor or in memory depending on the architecture style.

Efficiency Comparison

Assuming a 16-bit memory address and data operands, and 16 general-purpose registers for the Load-store architecture, the memory efficiency can be measured by calculating the total number of instruction bytes fetched and the total bytes of data transferred from/to memory. The architecture that results in the least total memory traffic is considered the most efficient.

Answer 2

The memory efficiency of different styles of instruction set architectures can be compared based on the memory traffic (code+data) they generate. The stack architecture is the most memory efficient, while the accumulator architecture requires frequent memory accesses, resulting in high memory traffic. The load-store and memory-memory architectures also have improved memory efficiency compared to the accumulator architecture.

Step-by-step explanation:

The memory efficiency of the four different styles of instruction set architectures can be compared based on the memory traffic (code+data) they generate.

1. Accumulator Architecture:

The assembly language code for the given high-level code sequence 'A=B+C, B=A+C, D=A-B' in accumulator architecture would be:

LOAD B

ADD C

STORE A

LOAD A

ADD C

STORE B

SUBTRACT B

STORE D

In this architecture, the operand values are frequently loaded from memory, leading to high memory traffic.

2. Memory-Memory Architecture:

The assembly language code for the given high-level code sequence 'A=B+C, B=A+C, D=A-B' in memory-memory architecture would be:

LOAD A, R1

LOAD B, R2

ADD R2, R3

STORE R3, A

LOAD A, R1

ADD R3, R4

STORE R4, B

SUBTRACT R2, R3

STORE R3, D

In this architecture, the operand values are frequently loaded and stored into registers, reducing memory traffic.

3. Stack Architecture:

The assembly language code for the given high-level code sequence 'A=B+C, B=A+C, D=A-B' in stack architecture would be:

PUSH A

PUSH B

ADD

POP A

PUSH A

ADD

POP B

SUBTRACT

POP D

In this architecture, the operand values are pushed onto the stack and operated upon, minimizing memory traffic.

4. Load-Store Architecture:

The assembly language code for the given high-level code sequence 'A=B+C, B=A+C, D=A-B' in load-store architecture would be:

LOAD B, R1

LOAD C, R2

ADD R1, R2, R3

STORE R3, A

LOAD A, R1

LOAD C, R2

ADD R1, R2, R4

STORE R4, B

LOAD A, R1

LOAD B, R2

SUBTRACT R1, R2, R3

STORE R3, D

In this architecture, the operand values are loaded into registers, and computations are performed, resulting in reduced memory traffic.

Comparing memory efficiency: The stack architecture is most efficient as it minimizes memory traffic by operating on the top of the stack, whereas accumulator architecture shows the highest memory traffic due to frequent memory accesses. Load-store and memory-memory architectures also have improved memory efficiency compared to the accumulator architecture but are less efficient than the stack architecture.