Question

Consider the fragment of RISC-V assembly below:

sd x29, 12(x16)
ld x29, 8(x16)
sub x17, x15, x14
beqz x17, label
add x15, x11, x14
sub x15, x30, x14
Suppose we modify the pipeline so that it has only one memory (that handles both instructions and data). In this case, there will be a structural hazard every time a program needs to fetch an instruction during the same cycle in which another instruction accesses data.

Draw a pipeline diagram to show were the code above will stall.
In general, is it possible to reduce the number of stalls/NOPs resulting from this structural hazard by reordering code?
Must this structural hazard be handled in hardware? We have seen that data hazards can be eliminated by adding NOPs to the code. Can you do the same with this structural hazard? If so, explain how. If not, explain why not.
Approximately how many stalls would you expect this structural hazard to generate in a typical program?

Answer 1

Reordering code can reduce but not eliminate stalls caused by structural hazards due to the hardware limitations of a single memory unit in a pipeline. Adding NOPs is not effective for resolving structural hazards, and hardware changes are usually required.

Step-by-step explanation:

The question you've asked is about how a structural hazard in a pipeline with a single memory that handles both instructions and data would affect the given RISC-V assembly code and how we could minimize stalls resulting from this issue. Structural hazards occur when hardware resources are insufficient to perform the needed tasks in the current pipeline stage.

Unfortunately, without a visual medium, I cannot draw a pipeline diagram here, but I can explain the scenario. Let's consider the stages of the pipeline: Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write Back (WB). The structural hazard occurs when the MEM stage for a data access overlaps with the IF stage for an instruction fetch, as they both need the memory unit at the same time.

In this scenario, the pipeline will stall at the instruction 'ld x29, 8(x16)' because it is a memory access operation immediately after another memory access operation 'sd x29, 12(x16)'. To address this, one approach could be to reorder the code to separate memory operations with operations that do not require memory access. However, code reordering might not always be possible due to dependencies between instructions.

Stalls can be minimally reduced by reordering the code, but not entirely avoided without changing hardware configurations. It is also impractical to add NOPs to resolve structural hazards, as this would not alleviate the underlying hardware limitation. In typical programs, the number of stalls depends on the frequency of instruction fetches overlapping with memory access operations. Using reordering, some stalls can be reduced, but in most cases, resolving structural hazards would involve making hardware changes, such as adding separate memories for instruction fetches and data accesses.