The p/n ratio that minimizes average delay in a logic gate is the square root of the ratio that equalizes rise and fall delays due to the relationship between intrinsic delay and output transition times.
The relationship between the p/n (pull-up to pull-down) ratio and the average delay in a logic gate is influenced by the trade-off between rising and falling delays. In digital circuits, the p/n ratio affects the strength of the pull-up and pull-down transistors, influencing the time it takes for a signal to transition from low to high (falling delay) or high to low (rising delay).
When the p/n ratio is adjusted, it has a significant impact on the gate's intrinsic delay. To minimize the average delay, designers seek to balance the rising and falling delays. Interestingly, it is observed that the p/n ratio providing the lowest average delay is the square root of the ratio that equalizes the rise and fall delays. This connection arises from the interplay between the transistor sizes, the charging and discharging of the load capacitance, and the overall speed of the logic gate. Achieving equal rise and fall delays is often a desirable goal to optimize the gate's performance in terms of speed and efficiency.