Question

Suppose that loads constitute 25% of the typical instruction mix on a certain machine. Suppose further that 15% of these loads miss in the last level of on-chip cache, with a penalty of 120 cycles to reach main memory. What is the contribution of last-level cache misses to the average number of cycles per instruction? You may assume that instruction fetches always hit in the Ll cache. Now suppose that we add an off-chip (L3 or L4) cache that can satisfy 90% of the misses from the last-level on-chip cache, at a penalty of only 30 cycles. What is the effect on cycles per instruction?

Answer 1

The initial last-level on-chip cache misses contribution to the average cycles per instruction is 4.5 cycles. Adding an off-chip cache that satisfies 90% of these misses at a penalty of 30 cycles reduces the contribution to 0.1125 cycles per instruction.

Step-by-step explanation:

The question asks about the impact of cache misses on the average cycles per instruction on a machine and the effect of adding an off-chip cache. Initially, loads represent 25% of the instruction mix, and 15% of these loads miss the last-level on-chip cache, with a 120-cycle penalty. To calculate the contribution of last-level cache misses to the average cycles per instruction (CPI), we use the following formula:

Miss rate × Penalty × Portion of loads = Contribution to CPI

The miss rate is 15%, the penalty is 120 cycles, and the portion of loads is 25%, so the contribution to CPI is given by:

0.15 (miss rate) × 120 (penalty) × 0.25 (portion of loads) = 4.5

The average contribution to CPI from last-level cache misses is 4.5 cycles per instruction.

With the addition of an off-chip cache, 90% of the misses from the last-level on-chip cache are satisfied with a lower penalty of 30 cycles. The effect on cycles per instruction can be calculated with the new miss rate and penalty:

0.15 (initial miss rate) × 0.10 (misses not satisfied by off-chip cache) × 30 (new penalty) × 0.25 (portion of loads) = 0.1125

The addition of the off-chip cache reduces the average contribution to CPI from last-level cache misses to 0.1125 cycles per instruction, significantly improving performance